National Repository of Grey Literature 4 records found  Search took 0.01 seconds. 
HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
Data stream compression and decompression methods.
Makedonenko, Oleksandr ; Kaczmarczyk, Václav (referee) ; Valach, Soběslav (advisor)
Cílem tento práce je prostudovat metody bezztrátové komprese a zmenšit datový tok ve komunikačním kanále, prováděním bezztrátové algoritmu komprese, který může být použity na FPGA desce s teoretickým dosahem rychlosti 1Gbit/s.
HLS development tool for DSP with custom programming language
Pastušek, Václav ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Nowadays, there are many different high-level syntheses for describing digital circuits. The best known ones generate VHDL code from programming languages such as ANSI C, C++, SystemC, SystemVerilog and MATLAB. But not everyone will identify with that type of programming, so sometimes it's good to go to a higher level of abstraction, where the internals of the components are hidden, and then the components are called with inputs and outputs. This thesis deals with the design of HLS, the design of input pseudocode, pseudo-libraries, compiler created in Python, its modules and practical application.
Data stream compression and decompression methods.
Makedonenko, Oleksandr ; Kaczmarczyk, Václav (referee) ; Valach, Soběslav (advisor)
Cílem tento práce je prostudovat metody bezztrátové komprese a zmenšit datový tok ve komunikačním kanále, prováděním bezztrátové algoritmu komprese, který může být použity na FPGA desce s teoretickým dosahem rychlosti 1Gbit/s.

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